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Generating an Output Clock PCI CD/CDa Configurable DMA Interface User’s Guide

10 EDT, Inc. May 2007

Generating an Output Clock

The PCI CD/CDa has a programmable frequency generator, allowing you to specify precisely the

frequency at which to transmit data.

PCI CDa

The PCI CDa has one programmable clock with a range of 168 Hz – 100 MHz. Most frequencies

between these extremes can be achieved with little error. (Some FPGA configuration files allow an

extended range of up to 200 MHz.)

The programmable clock is implemented with an ICS307-02 clock generator followed by a 14-bit

programmable divider. The reference clock to the ICS307-02 is 10.3861 MHz. For details on the

ICS307-02, consult Integrated Circuit Systems.

NOTE The library routine

set_ss_vco.c includes an example of setting the output clock frequency.

The following three library routines, documented in the EDT DMA Software Library, help compute the

output clock frequency:

edt_find_vco_frequency_ics307

Computes the PLL parameter for the ICS307 chip, based on an input clock

frequency and a target frequency.

edt_set_out_clk_ics307

Sets the frequency output using parameters computed by

edt_find_vco_frequency_ics307.

edt_set_frequency_ics307

A convenience function to to set the frequency on the desired channel by first

calling

edt_find_vco_frequency_ics307 or

edt_find_vco_frequency_ics307_nodivide, then edt_set_out_clk_ics307.

PCI CD

The output clock is generated from a phase-locked loop (PLL) oscillator, a reference crystal, and

programmable dividers. Because each of these components has physical limits, it may not be possible

to get exactly the frequency desired. To get the expected results, you need to understand how the

clock generator operates. Figure 1 diagrams how the final value is generated, using the following

notation:

xtal

10 MHz (PCI CD-20 or 30 MHz (PCI CD-60)

ref

The PLL reference frequency must be between 200 KHz and 5.0 MHz.

vco

The VCO output frequency must be between 50 MHz and 250 MHz.

fback

The VCO varies f

vco

until the feedback frequency matches the PLL reference frequency.

xilinx

The input frequency into the high speed odd divider must be less than 100 MHz.

low

The divide by n counter input frequency must be less than 30 MHz. If L and X are both set

to 1, then frequencies to 100 MHz can be passed to the final divide-by-two block.

out

This final divide by two assures a 50% output clock duty cycle.

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