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Registers PCI CD/CDa Configurable DMA Interface User’s Guide

30 EDT, Inc. May 2007

Stat Register

Size 8-bit

I/O read-only

Address 0x03

Access PCD_STAT

Stat Polarity Register

Size 8-bit

I/O read-write

Address 0x04

Access PCD_STAT_POLARITY

Bit PCD_ Description

7–4 STAT_INT Interrupt bits for the status bits. If the following conditions are both true, then the

corresponding bit of these four can be asserted to cause a PCI Bus interrupt:

• The device interrupt is enabled using the RMT_EN_INTR bit in the PCI Inter-

rupt and UI Xilinx Configuration Register.

• The corresponding bit is asserted in the Command Register (one of bits 7–4,

named STAT_INT_EN).

The PCI Bus interrupt is then caused when the corresponding STAT signal is

asserted according to the polarity specified in the Stat Polarity Register. To reset

the interrupt, disable and re-enable the appropriate STAT_INT_EN bit in the

Command Register.

3–0 STAT The state of user-definable STAT input signals as last sampled by the RXT clock

signal.

Bit PCD_ Description

7–6 not used

5 ENA_OUT_CTRL When set, enables the OUTPUT DISABLE signal on pin 22. (PCI CDa — not used)

4 STAT_INT_ENA Provides global enable or disable for all interrupt bits in Stat Register on page 30,

allowing the driver to disable and re-enable them in one operation, without altering

the state of the Stat register. This bit is used mainly by the driver to disable the Stat

interrupts to determine which other interrupts are pending. A value of 1 enables the

interrupts.

3–0 POLARITY A value of 0 indicates that a change from 0 to 1 from one clock cycle to the next

causes an interrupt in bits 7–4 of the Stat Register on page 30, if the corresponding

STAT_INT_EN bit is also enabled in the Command Register on page 28.

A value of 1 causes the same event when the STAT_INT bit changes from 1 to 0

from one clock cycle to the next.

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CDA CD 60 Guía de usuario Pagina 34