CDA CD 60 Especificaciones descargar pdf (Pagina 55)

PCI CD and PCI CDa

Document Number: 008-00965-06 EDT Public Revision: I December 2004

Template: edt.dot

Page 55

PCI CD Output Clock Generation

The output clock is generated from a phase-locked loop (PLL) oscillator, a reference crystal, and

programmable dividers. Because each of these components has physical limits to its operation, it may

not be possible to get exactly the frequency desired. To get the expected results, you need to understand

how the clock generator operates. Figure 1 diagrams how the final value is generated.

Figure 1 Legend

Frequency values:

xtal

PCI CD-20 is 10 MHz, PCI CD-40 is 20 MHz, and PCI CD-60 is 30 MHz.

ref

The PLL reference frequency must be between 200 KHz and 5.0 MHz.

vco

The VCO output frequency must be between 50 MHz and 250 MHz.

fback

The VCO varies f

vco

until the feedback frequency matches the PLL reference frequency.

xilinx

The input frequency into the high speed odd divider must be less than 100 MHz.

low

The divide by n counter input frequency must be less than 30 MHz. If L and X are both set to 1,

then frequencies to 100 MHz may be passed to the divide by 2.

out

This final divide by 2 assures a 50% output clock duty cycle.

Figure 1. Output Clock Generation Block Diagram

The formula for calculating f

out

is:

out

= (N * V * f

xtal

)/(m * R * H * L * X * 2)

feedback

prescale

V=1 or 8

feedback divider

=3 to 127

reference divider

M=3 to 127

crystal

oscillator

VCO

VCO output

divider

R=1, 2, 4, or 8

high-speed

odd divider

H=1, 3, 5, or 7

first divide

L=1 to 64

X=1 to 256

divide by 2

for clock

symmetry

second

divide b

xtal

ref

vco

xilinx

low

out

fback

1 2 ... 50 51 52 53 54 55 56 57 58 59 60 ... 90 91

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