CDA CD 60 Especificaciones descargar pdf (Pagina 59)

PCI CD and PCI CDa

Document Number: 008-00965-06 EDT Public Revision: I December 2004

Template: edt.dot

Page 59

PCI CDa Output Clock Generation

The PCI CDa has one programmable clock with a range of 168 Hz to 100 MHz. Most frequencies

between these extremes can be achieved with little error. (Some FPGA bitfiles may allow an extended

range of up to 200 MHz.)

The programmable clock has an ICS307-02 clock generator (from Integrated Circuit Systems,

www.icst.com

) followed by a 14-bit programmable divider. The reference clock to the ICS307-02 is

10.3861 MHz.

Note: Seee set_ss_vco.c as an example.

The following three routines provided by EDT handle the clock generators:

edt_find_vco_frequency_ics307

Description

Computes the PLL parameter for the ICS307 chip, based on an input clock frequency (xtal)

and a target frequency (target). The EdtDev pointer is not required; it can be set to NULL. If

the xtal value is 0, there should be an EdtDev pointer that can be used to determine the

reference clock frequency.

The nodivide version turns off the final divide by 2 in the FPGA code; if the current bitfile

supports that, frequencies greater than 100 MHz can be targeted.

Syntax

#include “edtinc.h”

#include “edt_ss_vco.h”

double edt_find_vco_frequency_ics307(EdtDev *edt_p, double

target, double xtal, edt_pll *pll, int verbose)

double edt_find_vco_frequency_ics307_nodivide(EdtDev *edt_p,

double target, double xtal, edt_pll *pll, int verbose)

Arguments

edt_p

Device handle returned from

edt_open.

target

Desired output frequency in Hz.

xtal

The base frequency of the PCI SS board. Default is 10.3681 MHz.

verbose A value of 1 prints a summary of the results to

stdout. A value of 0 turns

off output.

Return

The return value is the actual frequency found that comes closest to the target frequency. The

PLL structure returns the values required for edt_set_frequency_ics307.

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