CDA CD 60 Especificaciones descargar pdf (Pagina 79)

PCI CD and PCI CDa

Document Number: 008-00965-06 EDT Public December 2004

Template: edt.dot

Page 79

D24 BURST_EN

A value of 0 means bytes are written to memory as soon as

they are received. A value of 1 means bytes are saved to

write the most efficient number at once.

D23 MN_DMA_DONE

Read only: a value of 1 indicates that the main DMA is not

active.

D22 MN_NXT_EMP

Read only: a value of 1 indicates that the main DMA next

address and next count registers are empty.

D21–19

Reserved for EDT internal use.

D18 PG_INT

Read-only: a value of 1 indicates that the page interrupt is

set (enabled by bit 28 of this register), and that the main

DMA has completed transferring a page for which bit 16

(the page interrupt bit) was set in the scatter-gather DMA

list (see Figure 6). If the PCI interrupt is enabled (bit 15 of

the PCI interrupt and remote Xilinx configuration register),

this bit causes a PCI interrupt.

Clear this bit by disabling the page done interrupt (bit 28 of

this register).

D17 CURPG_INT

Read-only: a value of 1 indicates that bit 16, the page

interrupt bit, was set in the scatter-gather DMA list entry for

the current main DMA page.

D16 NXTPG_INT

Read-only: a value of 1 indicates that bit 16, the page

interrupt bit, was set in the scatter-gather DMA list entry for

the next main DMA page.

D15–0

The number of bytes in the next scatter-gather DMA list.

Flash ROM Access Registers

Flash ROM Address Register

Size 32-bit

I/O read-write

Address 0x80

Access EDT_FLASHROM_ADDR

Comment Use this register and the flash ROM data register (below) to update the

program in the field-programmable gate array that implements the PCI

interface.

Bit Description

D31–25 Reserved for EDT internal use.

1 2 ... 74 75 76 77 78 79 80 81 82 83 84 ... 90 91

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