
PCI CD and PCI CDa
Document Number: 008-00965-06 EDT Public December 2004
Template: edt.dot
Page 77
Scatter-gather DMA Next Address Register
Size 32-bit
I/O read-write
Address 0x14
Access EDT_SG_NXT_ADDR
Comments The driver software writes this register as described in step 2 of the list in the
Performing DMA section on page 74.
Bit Description
A31–0 The starting address of the next DMA.
Scatter-gather DMA Current Count and Control Register
Size 32-bit
I/O read-only
Address 0x18
Access EDT_SG_CUR_CNT
Comments The driver software can read this register for debugging or to monitor DMA
progress.
Bit Description
A31–16 Read-only versions of bits 31–16 of the scatter-gather DMA next count and
control register.
D15–0 The number of words still to be transferred in the current DMA.
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