
PCI CD and PCI CDa
Document Number: 008-00965-06 EDT Public December 2004
Template: edt.dot
Page 82
The programming has failed if it has not completed after 32 clock cycles.
PCI Interrupt Status Register
Size 32-bit
I/O read-only
Address 0xC8
Access EDT_DMA_STATUS
Comments The driver uses this register initially to determine the source of a PCI
interrupt.
Bit EDT_ Description
D16–31 Not used.
D15 PCI_INTR PCI interrupt. When asserted, the PCI CD is asserting an
interrupt on the PCI bus.
D14 Not used.
D13 RMT_INTR Remote Xilinx interrupt. When asserted, the remote Xilinx
interrupt is set. If bits 14 and 15 of the the PCI interrupt and
remote Xilinx configuration register are aserted, the remote
Xilinx causes a PCI interrupt.
D12 DMA_INTR End of DMA interrupt. Asserted when at least one of the
DMA interrupts is asserted in the scatter-gather DMA next
count and control register. Causes a PCI interrupt if bit 15
of the PCI interrupt and remote Xilinx configuration register
is enabled.
D11–0 Not used.
Remote Xilinx Registers
The Xilinx chip is a programmable integrated circuit used to implement the PCI CD interface or to test
the board. The Xilinx programmable IC is programmed serially, using the PCI interrupt and remote
Xilinx configuration register as described on page 81.
Note
The following registers are defined to control the interface and reside in the remote Xilinx IC.
In order to access those registers, the PCI CD requires that the remote Xilinx be loaded with a
program that defines them. If the Xilinx is not loaded, or loaded with a different program, these
registers are inaccessible.
The Xilinx IC is programmed when the PCI CD driver is loaded, or by the application program.
If you have received a customized application program for your PCI CD from Engineering
Design Team,some or all of these registers may not be defined. Consult the documentation
that came with your customized program instead.
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